@techreport{TR-IC-13-34,
   number = {IC-13-34},
   author  =  {{C}aio  {H}offman  and  {L}uiz {E}. da {S}. {R}amos and
                   {R}odolfo  {J}.  de {A}zevedo and {G}uido {C}. {S}.
                   de {A}raújo},
   title  =  {{I}mproving  the  {M}odeling  and  {A}nalysis of {E}rror
                   {C}orrection   {T}echniques   for  {P}hase-{C}hange 
                   {M}emory},
   month = {{D}ecember},
   year = {2013},
   institution   =   {{I}nstitute   of  {C}omputing,  {U}niversity  of 
                   {C}ampinas},
   note = {In English, 21 pages.
    \par\selectlanguage{english}\textbf{Abstract}
       Due  to  projections  of  high scalability, Phase-Change Memory
       (PCM)  is  seen  as  a new main memory for computer systems. In
       fact,  PCM  may  even  replace  DRAM, whose scaling limitations
       require new lithography technologies that are still unknown. On
       the  down-side,  PCM has low endurance when compared with DRAM,
       i.e.,  on  average,  a  PCM  cell  can  only  withstand  $10^8$ 
       bit-flips  (modification  of stored bit values) before the cell
       fails.   To  address  PCM's  low  endurance,  Error  Correction 
       Techniques  (ECTs)  have been proposed, which aim at increasing
       PCM's  lifetime.  However,  previous  lifetime analyses of ECTs
       have   not  considered  the  difference  between  the  bit-flip 
       frequencies  of data bits and code bits (used to correct errors
       in  data  bits).  That  observation  is crucial for the correct
       analysis  of  the  ECTs since high bit-flip frequencies lead to
       faster  wear-out.  \par  In  this work, we improve the wear-out
       analysis   of  PCM  by  modeling  and  analyzing  the  bit-flip 
       probabilities  of  five  ECTs, namely, ECP, DRM, SECDED, SAFER,
       and  FREE-p. We then use our analysis to evaluate the impact of
       error correction on the wear-out of PCM. To do our analyses, we
       mathematically  modeled  and  simulated  the  ECTs using both a
       theoretical   bit-flip  probability  (50\%)  and  an  empirical 
       bit-flip  rate  (15\%),  obtained  from  the  execution of SPEC
       CPU2006.  Our  results  show  clear  endurance  degradation  in 
       techniques  that  use error-correcting codes, which contradicts
       some  previous  results in the literature. Finally, we analyzed
       the power consumption of the ECTs, and found that ECP and SAFER
       exhibit the best trade-off between endurance and write energy.
  }
}