library std;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity tb_contador_base is
  
end tb_contador_base;


architecture behavior of tb_contador_base is

  constant clk_period : time := 100 ns;  -- Clock period
  constant delta : time := clk_period / 10;  -- Delta time to assert the inputs

  file InFile        : text open read_mode is "contador.base.input";  -- Input file
  file OutFile       : text open write_mode is "contador.base.output";  -- Output file
  file FullFile      : text open write_mode is "contador.base.full.output";  -- Full output

  signal end_of_file : boolean;  	-- End of File indicator

  signal iclk	     : std_logic := '0';		-- Internal Clock (testbench only)
  signal iresetn     : std_logic;		-- Internal Resetn (testbench only)
  signal clk	     : std_logic;		-- Clock signal
  signal resetn	     : std_logic;
  signal sensor : std_logic_vector(0 to 4);
  signal total : natural;

  component contador
    port (
      clk    : in  std_logic;
      resetn : in  std_logic;
      sensor : in  std_logic_vector(0 to 4);
      total  : out natural);
  end component;
  
  
begin  -- behavior

  iclk <= not iclk after clk_period / 2;
  iresetn <= '0', '1' after 7 * clk_period;

  contador0: contador
    port map (
      clk    => clk,
      resetn => resetn,
      sensor => sensor,
      total  => total);
  
  ReadInput : process(iClk, iResetn)

    variable input_line	  : line;
    variable clk_value	  : std_logic;
    variable resetn_value : std_logic;
    variable sensor_value : std_logic_vector(0 to 4);
     
  begin  -- process ReadInput
    if (iResetn = '0') then
      end_of_file <= false;

    elsif iClk'EVENT and iClk = '0' then
      if EndFile(InFile) then
	end_of_file <= true;  		-- stop when reaches end of file
      else
	ReadLine(InFile, input_line);

	Read(input_line, clk_value);
	Read(input_line, resetn_value);
	Read(input_line, sensor_value);
	
	sensor <= sensor_value after delta;
	resetn <= resetn_value after delta;
	clk <= clk_value;
      end if;
    end if;

  end process ReadInput;

  -- Writes a simple output report
  WriteOutput : process(Clk, Resetn)

    variable output_line : line;
    variable command     : character;  	-- Input command

  begin  -- process ReadInput
    if (Resetn = '0') then
      null;
    elsif Clk'EVENT and Clk = '0' then
      Write(output_line, now, left, 12);
      Write(output_line, total, left, 4);
      WriteLine(OutFile, output_line);
    end if;
  end process WriteOutput;
  

  -- Writes an extende output report (including the input)
  WriteFull : process(iClk, iResetn)

    variable output_line : line;
    variable command     : character;  	-- Input command

  begin  -- process ReadInput
    if (iResetn = '0') then
      null;
    elsif iClk'EVENT and iClk = '0' then
      Write(output_line, now, left, 11);
      Write(output_line, sensor, left, 6);
      Write(output_line, total, left, 5);
      WriteLine(FullFile, output_line);
    end if;
  end process WriteFull;

  -- stop the simulator when the end of file is reached
  assert not end_of_file report "End of Simulation" severity failure;

end behavior;