LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;


ENTITY tb_alu IS

END tb_alu;
ARCHITECTURE Bhv OF tb_alu IS


  constant clk_period : time := 100 ns;  -- Clock period
  constant delta : time := clk_period / 10;  -- Delta time to assert the inputs

  file InFile        : text open read_mode  is "alu.in";   -- Input file
  file OutFile       : text open write_mode is "alu.out";  -- Output file

  signal SrcA       : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0') ;
  signal SrcB       : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
  signal AluControl : STD_LOGIC_VECTOR(2 DOWNTO 0)  := (others => '0');
  signal AluResult  : STD_LOGIC_VECTOR(31 DOWNTO 0);
  signal Zero       : STD_LOGIC;
  signal Overflow   : STD_LOGIC;
  signal CarryOut   : STD_LOGIC;
  

  signal clk : STD_LOGIC := '1';
-- signal erro : boolean := false;

  
  Component ALU IS
   PORT (SrcA       : IN   STD_LOGIC_VECTOR(31 DOWNTO 0);
         SrcB       : IN   STD_LOGIC_VECTOR(31 DOWNTO 0);
         AluControl : IN   STD_LOGIC_VECTOR(2 DOWNTO 0);
         AluResult  : OUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
         Zero       : OUT  STD_LOGIC;
         Overflow   : OUT  STD_LOGIC;
         CarryOut   : OUT  STD_LOGIC);
  END Component Alu;
  
begin 
 
alu_0: ALU port map (Srca, SrcB, AluControl, AluResult, Zero, Overflow, CarryOut);


clk <= not clk after clk_period / 2;    -- gera sinal de clock


-- Leitura do Arquivo de Entrada
ReadInput : process(clk)               

    variable input_line   : line;
    variable SrcA_f       : STD_LOGIC_VECTOR(31 DOWNTO 0);
    variable SrcB_f       : STD_LOGIC_VECTOR(31 DOWNTO 0);
    variable AluControl_f : STD_LOGIC_VECTOR(2 DOWNTO 0);
     
  begin  -- process ReadInput
    if clk'EVENT and clk = '1' then
      if EndFile(InFile) then
-- stop the simulator when the end of file is reached
  	assert false report "End of Simulation" severity failure;
      else
	ReadLine(InFile, input_line);
	Read(input_line,AluControl_f);
	Read(input_line,SrcA_f);
	Read(input_line,SrcB_f);
	
	AluControl <= AluControl_f after delta;
	SrcA <= SrcA_f after delta;
	SrcB <= SrcB_f after delta;        
      end if;
    end if;

  end process ReadInput;

-- Escrita no Arquivo de Saida
WriteOutput : process(clk)

    variable output_line : line;
    variable command     : character;  	-- Input command

  begin  -- process ReadInput
    if clk'EVENT and clk = '1' then
      Write(output_line, now, left, 12);  -- escreve tempo de simulação
      Write(output_line, AluResult, left, 35);
      Write(output_line, Zero, left, 3);
      Write(output_line, Overflow, left, 3);
      Write(output_line, CarryOut, left, 3);     
      WriteLine(OutFile, output_line);
    end if;
  end process WriteOutput;



END Bhv;