X_DES
DES Cryptoprocessor

Function Description

This core is a fully compliant implementation of the DES encryption algorithm. Both encryption and decryption are supported. ECB, CBC and triple DES versions are available. Simple, fully synchronous design with low gate count.

Symbol

Features

Pin Description

Name
Type
Description
RES_N
Input
Core reset, active low.
CLK
Input
Core clock signal.
START
Input
It indicates the start of encryption or decryption.
E_D
Input
Selects encryption or decryption.
KEY[63:0]
Input
Input key.
DIN[63:0]
Output
Input data.
DOUT[63:0]
Output
Output data.
READY
Output
Output data valid.

Functional Description

This core performs data encryption and decryption according to the DES algorithm. The E_D input port selects encryption or decryption behavior. A pulse on the START port triggers the beginning of a cryptographic operation on the data DIN using the KEY as key. Only 56 of the 64 bits of the KEY input port are considered by the core, according to the DES algorithm. After 16 clock cycles, the READY output indicates that the output value DOUT is valid. The core is immediately ready for another operation so that a throughput of 64 bits every 16 cycles can be sustained.
The CBC version requires extra pins to set initial conditions. The triple DES version requires a higher latency.

Deliverables

Synthesizable Verilog RTL.
Testbench.
Complete data sheet.