X_DCT
Discrete Cosine Transform Synthesizable Core
This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples. The simple, fully synchronous design allows for fast operation while maintaining a low gate count. It offers high performance and many features to meet your multimedia, digital video and digital printing applications.
This core can perform both Discrete Cosine Transform (DCT) and its inverse (IDCT) on a 8X8 block of samples. The mathematical definition for the DCT and IDCT are shown below.
In order to operate, this core must be connected to a 64x15 dual port RAM. This memory is written synchronously and read asynchronously.
Input samples are provided to the XH port, while transformation result are available from port YV. If we consider a block of samples as shown below, the input port XH accepts rows of samples. This means that input samples are to be provided in the order X00, X01,..., X07, X10,...., X70,...., X77.
Port YV outputs transformed samples as columns (i.e. Y00,Y10,...,Y70,Y01,...,Y07,...,Y77) after a latency period of approximately 64 clock cycles.
A clock cycle wide pulse on the START input indicates the very first sample X00 of a series of blocks that need to be transformed.
The IDCT pin selects the type of transform to be performed on the input samples, DCT or IDCT. This input must be stable from the input sample X00 until at least the output sample Y77.
DCT/IDCT is a typical building block for image processing, printers, desktop video editing, digital still cameras, surveillance systems, and video conferencing cores.
