Function Description

The HDLC Controller handles bit oriented protocol structure and formats the data as per the packet switching protocol defined in the X.25 (Level 2) recommendations of the CCITT. It transmits and receives the packeted data (information or control) serially in a format shown in the figure below, while providing the data transparency by zero insertion and deletion. It generates and detects the flags. Further, it provides 16 or 32 bit cyclic redundancy check on the data packets using the CCITT defined polynomial. In addition, it recognizes a single byte address in the received frame.

Features

• Formats data as per X.25 (CCITT) level-2 standards
• Single byte address recognition
• 16 -bit and 32-bit frame check sequence (CRC)
• High speed serially clocked output. The data rate is equal to the clock rate.
• Delivered as synthesizable VHDL code
• Motorola M6800 microprocessor interface
• Software reset
• Supports multiplexing of multiple HDLCs
• Internal registers for buffering

Symbol

Pin Description

Signal name	Mode	Function
RST	Input	Reset input. Active LOW reset input which resets all the registers.
CKI	Input	Clock input. Bit Rate clock in the External Timing Mode. It is used for shifting the formatted packets in and out.
E	Input	Enable clock. Activates the address bus and R/W input and enables data transfers on the data bus.
CS	Input	Chip select. Active LOW chip select to enable read or write operations to the registers in the HDLC.
CDSTI	Input	The serial data input line.
A(3:0)	Input	Address bus inputs. The internal registers are selected in conjunction with CS, and R/W inputs, and ENA clock.
R/W	Input	Read/write control for microcontroller readable/writable registers.
DIN(7:0)	Input	Microprocessor input data bus. Allows the data transfer from the microprocessor to the HDLC controller.
DOUT(7:0)	Output	Microprocessor output data bus. Allows the data transfer from the HDLC controller to the microprocessor.
IRQ	Output	Interrupt request output.
CDSTO	Output	The serial data output line.

Block Diagram

M6800 Processor Interface

Handles the reading and writing actions of the M6800 microprocessor.

Registers

Includes all the microprocessor controllable registers.

Receiver block

Receives the serial data, and stores it to the receiver buffer register.

Transmit block

Transmits the parallel data from the transmit buffer register to the serial output line TXD.

Interrupt Control

Handles the interrupts of HDLC controller.

 

Applications

• Data link controllers and protocol generators
• Digital sets, PBXs and private packet networks
• D-channel controller for ISDN basic access

Deliverables

• HDL RTL source code
• Testbench
• Example testbench wrapper for post-route simulation
• Vectors for testbench
• Simulation script
• Synthesis script
• Expected results for testbench
  

Core Modifications

The HDLC core can easily be customized to include:

• The processor interface can be modified for customer’s needs
• Enabling/disabling functions for transmitter and receiver
• Abort sequence