MC 542 - Classes #, A and B
Computer Organization: Theory and Practice

2011

classrooms	Project Manager	Evaluation	Exercises	Jobs	REFERENCES	Questions and answers	Calendar	Slides	Students	Notes

Contact Us

Teacher: Paulo Cesar Centoducatte (Email) - Room 11 - IC-1

PED:         Raphael Zinslypdf   pdf-6

OBS .:   When sending an email please put in the subject "mc542"

Notices

Data	Notice
15/09	Laboratory Class
18/08	Included in useful links: All About Circuits! ("This site provides a series of online textbooks covering electricity and electronics. The information provided is great for both students and hobbyists who are looking to expand their knowledge in this field. These textbooks were written by Tony R. Kuphaldt and released under the Design Science License. ")
17/08	Em Slides you can find pdf files in versions 1 and 6 slides per page
09/08	The classroom moved from 361 to 316

classrooms

Class #AB
         Monday: 16:00 - 18:00 - Room: 316
         Wednesdays:    16:00 - 18:00 - Room: 316
         Fridays:        16:00 - 18:00 - Room: 316 and / or CC02-CC03 (IC-03)

Project Manager

Professor:
Room 11 of IC 1 - Prof. Paulo C. Centoducatte
(schedule day and time by email)

Evaluation

Race 1 (P1): Weight 4

Race 2 (P2): Weight 6

Exam --

Exercises (Hey)
Project (Prj)
MP -- Average of Tests P1 and P2
MTP -- Average of Exercises and Project
MMC542 -- Weighted Average in MC542 Course
Ex - Final Exam Note
NF - Final grade

MP = (4P1 + 6P2) / 10

$\ begin {displaymath} M_ {TP} = \ frac {\ frac {\ sum_ {1} ^ {n} E_ {i}} {n} + Prj} {2} \ end {displaymath}$

$\ begin {displaymath} M_ {MC542} = \ left \ {$

invoice = MMC542 se MMC542 Bigger or equal a 5,0

invoice = (MMC542 + EX) / 2 if the student is
with weighted average (MMC542) less
that 5,0 and has frequency greater or
equal to 75%.

Jobs

Students should do a series of Practical Exercises and a Project in the semester:

Exercise 1: - individual

Delivery: until 8:00 am

Exercise 2: -- individually

Delivery fee: until 8:00 am

Project 1: -- Group of up to three students

Submit: at - List of group members
Delivery: until 24:00

The practical exercises and the project must be delivered in the indicated date.

OBS .: The work delivered up to 24 hours after the indicated deadline will not suffer a penalty. After this grace period is over, only the work delivered within 72 hours will be accepted after the indicated deadline, for which there will be a penalty of 30% of the maximum amount.

Recommended VHDL and project documents:

Altera: Recommended HDL Coding Styles

Actel HDL Coding Style Guide

The Ten Commandments of Excellent Design

The Ten Commandments of Excellent Design VHDL Code Examples

Recommended Exercises

Digital Design and Computer Architecture

Chapter 1: 1.4; 1.6 to 1.13; 1.15 to 1.17; 1.19; 1.21; 1.25 to 1.31; 1.33 to 1.36; 1.39; 1.41; 1.42; 1.48 to 1.51; 1.60 to 1.63
Chapter 2: 2.1 to 2.3; 2.7 to 2.9; 2.12 to 2.18; 2.21; 2.24 to 2.26; 2.28 to 2.30; 2.32
Chapter 3: 3.1 to 3.7; 3.9 to 3.12; 3.15 to 3.17; 3.19 to 3.21
Chapter 5: 5.1, 5.3; 5.8; 5.18; 5.20 to 5.29; 5.36 to 5.39; 5.45
Chapter 6: 6.1 to 6.4; 6.8; 6.9; 6.11; 6.12; 6.14; 6.24 to 6.26
Chapter 7: 7.1; 7.3 to 7.6; 7.8; 7.9; 7.12; 7.13; 7.24 to 7.29
Chapter 8: 8.1 to 8.12; 8.15 to 8.21

Fundamentals of Digital Logic with VHDL Design

Chapter 2: 2.1 to 2.27

Chapter 3: 3.1 to 3.13

Chapter 4: 4.1 to 4.20

Chapter 5: 5.1 to 5.10

Chapter 6: 6.1 to 6.17

Chapter 7: 7.1 to 7.24 (skipping VHDL exercises)

Chapter 8: Skip the VHDL

Computer Organization & Design, The Hardware / Software Interface.

Chapter 2: 2.1 to 2.5; 2.10 to 1.13; 2.15 to 2.22; 2.32; 2.44
Chapter 3: 3.1 to 3.6; 3.9; 3.12; 3.16; 3.20;
Cachapter 4: 4.1 to 4.6; 4.13; 4.17; 4.21; 4.23; 4.25 to 4.28; 4.32; 4.33; 4.40; 4.41; 4.43; 4.44; 4.50; 4.53; 4.57
Cachapter 5: 5.1; 5.4; 5.5 to 5.15; 5.17; 5.18; 5.20; 5.21; 5.22; 5.26
Chapter 6: 6.1 to 6.4; 6.7; 6.8; 6.11 to 6.16; 6.19 to 6.26; 6.28 to 6.31
Chapter 7: 7.1 to 7.23; 7.25 to 7.30; 7.32; 7.33; 7.35; 7.36

REFERENCES

Menus

Theory: Basic notions about logic circuits. Memories, central processing units. Addressing, bus, interruption, communications, interfaces and peripherals. Typical computers.
Practice: Digital design methodology. Design techniques using programmable logic. Electrical characteristics of digital circuits. VHDL Language Concepts. Design and implementation of combinational logic (decoders, selectors, etc.). Design and implementation of sequential logic (Flip-flops, Accountants, etc.). Arithmetic circuits. Memories. Design and implementation of a cpu.

Main References

David Harris and Sarah Harris. Digital Design and Computer Architecture. Morgan Kaufmann. ISBN: 978-0-12-370497-9

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. McGraw-Hill.
David A. Patterson & John L. Hennessy. Computer Organization & Design, The Hardware / Software Interface. Third Edition. Morgan Kaufmann.
David A. Patterson & John L. Hennessy. Computer Organization and Design. The Hardware / Software Interface. Third Edition.

Peter J. Ashenden. The VHDL Cookbook.
Actel HDL Coding Style Guide

Other References

M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals🇧🇷 Printece Hall.

John F. Wakerly. Digital Design: Principles & Pratices (second Edition)🇧🇷 Printece Hall.

Herbert Taub. Digital Circuits and Microprocessors. McGraw-Hill.

John P. Uyemura. Digital Systems an integrated approach. Thomson Pioneer.

Mehdi R. Zargham. Computer Architecture: Single and Parallel Systems🇧🇷 Printice Hall.

John P. Hayes. Computer Architecture and Organization. McGraw-Hill Series in Computer Organization and Architecture.

Fredrick J. Hill & Gerald R. Peterson. Digital Logic and Microprocessors. John Wiley & Sons.

Douglas V Hall. Digital Circuits and Systems. McGraw-Hill - Electronic Engineering Series.

Albert P. Malvino. Microcomputers and Microprocessors. Makron.

John L. Hennessy & David A. Patterson. Computer Architecture. The Quantitative Approach. Second Edition. Morgan Kaufmann

Course Program

David M. Harris and Sarah L. Harris. Digital Design and Computer Architecture. Morgan Kaufmann

Chapter 1:
Chapter 2:
Chapter 3:
Chapter 4:
Chapter 5: The VHDL part
Chapter 6:
Chapter 7:
Chapter 8:

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. mcgraw-hil

Chapter 1: Read only
Chapter 2: 2.1-2.7, 2.9.

Chapter 3: 3.1-3.3, 3.8.1, 3.8.3-3.9

Chapter 4: 4.1-4.6, 4.12

Chapter 5: 5.1-5.7

Chapter 6: 6.1-6.6

Chapter 7: 7.1-7.13

Chapter 8: 8.1-8.7
Chapter 9: 9.

David A. Patterson and John L. Hennessy. Computer Organization Design, The Hardware / Software Interface.Morgan Kaufmann

Chapter 1: Read only

Chapter 2: 2.1-2.5 (2.8 and 2.9 - reading)

Chapter 3: 3.1-3.8 (3.9 - reading)

Chapter 4: 4.1-4.8 (does not include the part already seen in logic circuits)

Chapter 5: 5.1-5.6
Chapter 6: 6.1-6.7 (6.8 - reading)
Chapter 7: 7.1-7.5
Chapter 8: 8.1-8.6

Useful links

Homepage of the Altera University Program.
Page for obtaining the Altera license
The VHDL Cookbook
Actel HDL Coding Style Guide
VHDL reference material
VHDL Tutorial
GHDL, GHDL Guide e GTKWAVE , Gtkwave guide (some linux distributions have gtkwave)
SPIM - MIPS simulator
Various simulators and tutorials

Calendar

Aula	Matter
August
(03) 1^a.	Presentation of the Course; Number Systems (pdf pdf-6)
(05) 2^a.	Number Systems (cont.); Logical Doors, Technology (pdf pdf-6)
(08) 3^a.	Logical Doors, Technology (cont.)
(10) 4^a.	Logical Doors, Technology (cont.); Combinational Circuits Project (pdf pdf-6)
(12) 5^a.	Combinational Circuits Project (cont.)
(15) 6^a.	Combinational Circuit Design (cont.) - Karnaugh Maps (MK)
(17) 7^a.	Combinational Circuits Project (cont.) - MK, don't care
(19) 8^a.	Combinational Circuits Project (cont.)
(22) 9^a.	Sequential Circuits (pdf pdf-6)
(24) 10^a.	Sequential Circuits (cont.)
(26) 11 ^a.	Sequential Circuits (cont.)
(29) 12^a.	Sequential Circuits (cont.) - design of finite-state machines (pdf pdf-6)
(31) 13^a.	Sequential Circuits (cont.) - elimination of redundant states (pdf pdf-6)
September
Aula	Matter
(02) 14^a.	Introduction to VHDL (pdf pdf-6)
(05) 15^a.	Introduction to VHDL
(07)	There will be no activities.
(09) 16^a.	Introduction to VHDL (cont.): Scope, components, configuration, pakage (pdf pdf-6)
(12) 17^a.	Introduction to VHDL (cont.): (pdf pdf-6)
(14) 18^a.	Introduction to VHDL (cont.):
(16) 19^a.	Lab class: In the directory Control (Seq) there are two .vhd files that will be used as an example of using the Quartus and ghdl and gtkwave tools and in Docs / usage-ghdl.txt a short text with the commands to analyze, elaborate, execute (simulate) and observe the waveforms generated during the example simulation. A tutorial for Quartus can be seen here
(19) 20^a.
(21) 21^a.
(23) 22^a.
(26) 23^a.
(28) 24^a.
(30) 25^a.
October
Aula	Matter
(03) 26^a.
(05) 27^a.
(07) 28^a.	Race 1 (Friday)
(10) 29^a.
(12)	There will be no activities.
(14) 30^a.
(17) 31^a.
(19) 32^a.
(21) 33^a.
(24) 34^a.
(26) 35^a.
(28)	There will be no activities.
(31) 36^a.
November
Aula	Matteryou can find pdf files in versions 1 and 6 slides per page
(02)	There will be no activities.
(04) 37^a.
(07) 38^a.
(09) 39^a.
(11) 40^a.
(14)	There will be no activities.
(16) 41^a.
(18) 42^a.
(21) 43^a.
(23) 44^a.
(25) 45^a.
(28) 46^a.
(30) 47^a.
December
Aula	Matter
(02) 48^a.	Race 2 (Friday)
(14)	Examination

Important Dates of Graduation Calendar.
30/09	Last day for dropping out of enrollment
11/10	Evaluation and discussion of courses
21/10	Last day for registration lock.
03/12	End of term.
12 - 17 / 12	Final exams.
19/12	Deadline for entry of media and frequencies.

MC 542 - Classes #, A and B Computer Organization: Theory and Practice

2011

Contact Us

MC 542 - Classes #, A and B
Computer Organization: Theory and Practice