MC 542 - Classes # and A
Computer Organization: Theory and Practice

2012S2

classrooms	Project Manager	Evaluation	Exercises	Jobs	REFERENCES	Questions and answers	Calendar	Slides	Students	Notes

Contact Us

Teacher: Paulo Cesar Centoducatte (Email) - Room 11 - IC-1

PED:       Bruno Leal Bastos

OBS .:   When sending an email please put in the subject "mc542"

Notices

Data	Notice
13/12	Spreadsheet available with notes of the exam
10/12	Exam: 12/12/2012 - 19:00 - Room CB08
08/12	Spreadsheet available with notes from the project
03/12	Spreadsheet available with notes from proof 2
26/11	The classes of 26 and 28/11/2012 will be in the laboratory (IC03)
23/11	Some tips for using GHDL can be found here
21/11	Project: Delivery until 06/12/2012 at 23:59
22/10	Spreadsheet available with notes from proof 1
16/10	Provided the statement of the project. See the processor specifications here SAP-1
04/10	Tips to stop simulation in ghdl - usage-ghdl.txt
27/08	Em Slides you can find pdf files in versions 1 and 6 slides per page

classrooms

Class A
         Monday: 19:00 - 21:00 - Room: CB08
         Wednesdays:    19:00 - 21:00 - Room: CB08
         Fridays:        19:00 - 21:00 - Room: 322 (CI-03) and / or CC02 (IC-03)

Project Manager

Professor:
Room 11 of IC 1 - Prof. Paulo C. Centoducatte
(schedule day and time by email)

Evaluation

Race 1 (P1): Weight 4 -- 15/10/2012

Race 2 (P2): Weight 6 -- 30/11/2012 ---- notes

Exam -- 12/12/2012

Exercises (Hey)
Project (Prj)
MP -- Average of Tests P1 and P2
NProject -- Project Note
MMC542 -- Weighted Average in MC542 Course
Ex - Final Exam Note
NFMC542 -- Final grade

-------------------------------------------------- -----------------------------------------

                                     MP = (4P1 + 6P2) / 10

----------------------------------------------------------------------------------

    MMC542 = (8MP + 2NProject) / 10 If MP > = 5,0 and NProject > = 5,0

    MMC542 = min (MFOR , NProject) If MP <5,0 or NT <5,0

-------------------------------------------------- ----------------------------------------

   NFMC722 = MMC542 se MMC542 > = 5,0

-------------------------------------------------- ---------------------------------------

invoice = (MMC542 + EX) / 2 if the student has weighted average
(MMC542) less than 5,0 and has frequency greater than or equal to
75%.

Jobs

Students should do a series of Practical Exercises and a Project in the semester:

Project: project.pdf SAP-1.PDF

Delivery: At 06/12/2012 at 23:59
Groups: here

The practical exercises and the project must be delivered in the indicated date.

OBS .: The work delivered up to 24 hours after
           indicated period will not suffer penalty. Exhausted this
           grace period, only the work delivered will be accepted
   up to 72 hours after the indicated deadline, for which
           there will be a penalty of 30% of the maximum amount.

Recommended VHDL and project documents:

Altera: Recommended HDL Coding Styles

Actel HDL Coding Style Guide

The Ten Commandments of Excellent Design

The Ten Commandments of Excellent Design VHDL Code Examples

Recommended Exercises

Digital Design and Computer Architecture (David Harris and Sarah Harris)

Chapter 1: 1.4; 1.6 to 1.13; 1.15 to 1.17; 1.19; 1.21; 1.25 to 1.31; 1.33 to 1.36; 1.39; 1.41; 1.42; 1.48 to 1.51; 1.60 to 1.63
Chapter 2: 2.1 to 2.3; 2.7 to 2.9; 2.12 to 2.18; 2.21; 2.24 to 2.26; 2.28 to 2.30; 2.32
Chapter 3: 3.1 to 3.7; 3.9 to 3.12; 3.15 to 3.17; 3.19 to 3.21
Chapter 5: 5.1, 5.3; 5.8; 5.18; 5.20 to 5.29; 5.36 to 5.39; 5.45
Chapter 6: 6.1 to 6.4; 6.8; 6.9; 6.11; 6.12; 6.14; 6.24 to 6.26
Chapter 7: 7.1; 7.3 to 7.6; 7.8; 7.9; 7.12; 7.13; 7.24 to 7.29
Chapter 8: 8.1 to 8.12; 8.15 to 8.21

Fundamentals of Digital Logic with VHDL Design (Stephen Brown and Zvonko Vranesic)

Chapter 2: 2.1 to 2.27

Chapter 3: 3.1 to 3.13

Chapter 4: 4.1 to 4.20

Chapter 5: 5.1 to 5.10

Chapter 6: 6.1 to 6.17

Chapter 7: 7.1 to 7.24 (skipping VHDL exercises)

Chapter 8: Skip the VHDL

Computer Organization & Design, The Hardware / Software Interfacesystem. (David A. Patterson & John L. Hennessy)

Chapter 2: 2.1 to 2.5; 2.10 to 1.13; 2.15 to 2.22; 2.32; 2.44
Chapter 3: 3.1 to 3.6; 3.9; 3.12; 3.16; 3.20;
Cachapter 4: 4.1 to 4.6; 4.13; 4.17; 4.21; 4.23; 4.25 to 4.28; 4.32; 4.33; 4.40; 4.41; 4.43; 4.44; 4.50; 4.53; 4.57
Cachapter 5: 5.1; 5.4; 5.5 to 5.15; 5.17; 5.18; 5.20; 5.21; 5.22; 5.26
Chapter 6: 6.1 to 6.4; 6.7; 6.8; 6.11 to 6.16; 6.19 to 6.26; 6.28 to 6.31
Chapter 7: 7.1 to 7.23; 7.25 to 7.30; 7.32; 7.33; 7.35; 7.36

REFERENCES

Menus

Theory: Basic notions about logic circuits. Memories, central processing units. Addressing, bus, interruption, communications, interfaces and peripherals. Typical computers.
Practice: Digital design methodology. Design techniques using programmable logic. Electrical characteristics of digital circuits. VHDL Language Concepts. Design and implementation of combinational logic (decoders, selectors, etc.). Design and implementation of sequential logic (Flip-flops, Accountants, etc.). Arithmetic circuits. Memories. Design and implementation of a cpu.

Main References

David Harris and Sarah Harris. Digital Design and Computer Architecture. Morgan Kaufmann. ISBN: 978-0-12-370497-9

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. McGraw-Hill.
David A. Patterson & John L. Hennessy. Computer Organization & Design, The Hardware / Software Interface. Third Edition. Morgan Kaufmann.
David A. Patterson & John L. Hennessy. Computer Organization and Design. The Hardware / Software Interface. Third Edition.

Peter J. Ashenden. The VHDL Cookbook.
Actel HDL Coding Style Guide

Other References

M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals🇧🇷 Printece Hall.

John F. Wakerly. Digital Design: Principles & Pratices (second Edition)🇧🇷 Printece Hall.

Herbert Taub. Digital Circuits and Microprocessors. McGraw-Hill.

John P. Uyemura. Digital Systems an integrated approach. Thomson Pioneer.

Mehdi R. Zargham. Computer Architecture: Single and Parallel Systems🇧🇷 Printice Hall.

John P. Hayes. Computer Architecture and Organization. McGraw-Hill Series in Computer Organization and Architecture.

Fredrick J. Hill & Gerald R. Peterson. Digital Logic and Microprocessors. John Wiley & Sons.

Douglas V Hall. Digital Circuits and Systems. McGraw-Hill - Electronic Engineering Series.

Albert P. Malvino. Microcomputers and Microprocessors. Makron.

John L. Hennessy & David A. Patterson. Computer Architecture. The Quantitative Approach. Second Edition. Morgan Kaufmann

Course Program

David M. Harris and Sarah L. Harris. Digital Design and Computer Architecture. Morgan Kaufmann

Chapter 1:
Chapter 2:
Chapter 3:
Chapter 4:
Chapter 5: The VHDL part
Chapter 6:
Chapter 7:
Chapter 8:

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. mcgraw-hil

Chapter 1: Read only
Chapter 2: 2.1-2.7, 2.9.

Chapter 3: 3.1-3.3, 3.8.1, 3.8.3-3.9

Chapter 4: 4.1-4.6, 4.12

Chapter 5: 5.1-5.7

Chapter 6: 6.1-6.6

Chapter 7: 7.1-7.13

Chapter 8: 8.1-8.7
Chapter 9: 9.

David A. Patterson and John L. Hennessy. Computer Organization Design, The Hardware / Software Interface.Morgan Kaufmann

Chapter 1: Read only

Chapter 2: 2.1-2.5 (2.8 and 2.9 - reading)

Chapter 3: 3.1-3.8 (3.9 - reading)

Chapter 4: 4.1-4.8 (does not include the part already seen in logic circuits)

Chapter 5: 5.1-5.6
Chapter 6: 6.1-6.7 (6.8 - reading)
Chapter 7: 7.1-7.5
Chapter 8: 8.1-8.6

Useful links

Homepage of the Altera University Program.
Page for obtaining the Altera license
The VHDL Cookbook
Actel HDL Coding Style Guide
VHDL reference material
VHDL Tutorial
GHDL, GHDL Guide e GTKWAVE , Gtkwave guide (some linux distributions have gtkwave)
SPIM - MIPS simulator
Various simulators and tutorials

Calendar

Aula	Matter
August
(01) 1^a.	Presentation of the course by prof. Rogério
(03)
(06) 2^a.	Course structure and computer architecture overview
(08) 3^a.	Logic doors ( pdf )
(10)
(13) 4^a.	Adders ( pdf )
(15) 5^a.	Registrars start ( pdf )
(17)
(20) 6^a.	Graphics
(22) 7^a.	8-bit systems architecture (arduino)
(24)
** (27) 8^a.	Technology (pdf pdf-6)
(29) 09^a.	Combinational Circuits Project (pdf pdf-6)
(31) 10^a.	Combinational Circuits Project (cont.)
September
Aula	Matter
(03) 11^a.	Combinational Circuits Project (Cont.) - Karnaugh Maps (MK), don't care
(05) 12^a.	Design of Combinational Circuits (Cont.) - Logical blocks (mux, decoder)
(07)	There will be no activities
(10) 13^a.	Sequential Circuits (pdf pdf-6) - latches and flip-flops
(12) 14^a.	Sequential Circuits (cont.)
(14) 15^a.	Sequential Circuits (cont.) - Synchronous and asynchronous counters
(17) 16^a.	Sequential Circuits (cont.) - Design of finite-state machines (pdf pdf-6)
(19) 17^a.	Sequential Circuits (cont.) - Design of finite-state machines (cont.)
(21) 18^a.	Sequential Circuits (cont.) - Exercises: design of state machines
(24) 19^a.	Sequential Circuits (cont.) - elimination of redundant states (pdf pdf-6)
(26) 20^a.	Introduction to VHDL (pdf pdf-6)
(28) 21^a.	Lab class: In the directory Control (Seq) there are two .vhd files that can be used as an example of using the ghdl and gtkwave tool and in Docs / usage-ghdl.txt a short text with the commands to analyze, elaborate, execute (simulate) and observe the waveforms generated during the simulation of the example.
October
Aula	Matter
(01) 22^a.	Introduction to VHDL (cont.)
(03) 23^a.	Introduction to VHDL (cont.)
(05) 24^a.	Introduction to VHDL (cont.) (pdf pdf-6; pdf pdf-6; pdf pdf-6;)
(08) 25^a.	Computer Architecture: Set of Instructions (pdf pdf-6)
(10) 26^a.	Computer Architecture: Instruction Set (cont.)
(12)	There will be no activities
(15) 27^a.	Test 1 --- notes
(17) 28^a.	Computer Architecture: Micro-Architecture (pdf pdf-6)
(19) 29^a.	Computer Architecture: Micro-Architecture (cont'd)
(22) 30^a.	Computer Architecture: Micro-Architecture - Pipeline (pdf pdf-6)
(24) 31^a.	Computer Architecture: Micro-Architecture - Pipeline (cont.)
(26) 32^a.	Computer Architecture: Micro-Architecture - Pipeline (cont.)
(29) 33^a.	Memory Hierarchy (pdf pdf-6)
(31) 34^a.	Memory Hierarchy (cont.)
November
Aula	Matter
(02)	There will be no activities
(05) 35^a	Memory Hierarchy (cont.)
(07) 36^a.	Memory hierarchy (cont.); Virtual Memory (pdf pdf-6)
(09) 37^a.	Laboratory Class
(12) 38^a.	Virtual Memory (pdf pdf-6)
(14) 39^a.	Virtual Memory (cont'd)
(16)	There will be no activities
(19)	There will be no activities
(21) 40^a.	Memory Protection with Virtual Memory
(23) 41^a.
(26) 42^a.
(28) 43^a.
(30) 44^a.	Exam 2
December
Aula	Matter
(03)
(05)
(07)
(12)	Examination

Important Dates of Graduation Calendar.
31/07	Start of classes for the 2nd semester of 2012
26/09	Last day for dropping out of enrollment
09/10	Evaluation and discussion of courses
17/10	Last day for locking the registration plate.
07/12	End of the 2012 term.
10 - 15 / 12	Final exams.
18/12	Deadline for entry of media and frequencies.

MC 542 - Classes # and A Computer Organization: Theory and Practice

2012S2

Contact Us

MC 542 - Classes # and A
Computer Organization: Theory and Practice