MC 542 - Class #
Computer Organization: Theory and Practice

2012

classrooms	Project Manager	Evaluation	Exercises	Jobs	REFERENCES	Questions and answers	Calendar	Slides	Students	Notes

Contact Us

Teacher: Paulo Cesar Centoducatte (Email) - Room 11 - IC-1

OBS .: When sending an email please put in the subject "mc542"

Notices

Data	Notice
17/07	Provided the notes of the exam
14/07	Exam: 16/07/2012; 20:00 pm; Room 361 IC 3 1/2
14/07	Provided the notes from work to day
05/07	Provided the notes the second test
11/06	Changed the date of Exam 2 (27/06 - 21h)
11/06	Provided the notes of the first test
02/05	The date of Exam 1 was changed (30/05 - 21:2 pm); Race 13 (06/21 - XNUMXh)
17/03	Defined the project. See the project specification here
17/03	The dates of Exam 1 (09/05 - 21h) and Exam 2 (13/06 - 21h) have been defined

classrooms

Class #

Project Manager

Professor:
Room 11 of IC 1 - Prof. Paulo C. Centoducatte
(schedule day and time by email)

Evaluation

Race 1 (P1): Weight 4

Order date: 30/05 - 21:00 to 23:00

Sala

Race 2 (P2): Weight 6

Order date: 27/06 - 21:00 to 23:00

Sala

Examination

Exercises (Hey)
Project (Prj)
MP -- Average of Tests P1 and P2
MTP -- Average of Exercises and Project
MMC542 -- Weighted Average in MC542 Course
Ex - Final Exam Note
NF - Final grade

   -------------------------------------------------- -----------------------------------------
   MP = (4P1 + 6P2) / 10

        MTP = (((E1 + ... + ANDk) / k) + Prj) / 2

     -------------------------------------------------- ---------------------------------------
MMC542 = (8MP + 2MTP) / 10 If MP > = 5,0 and MTP > = 5,0

MMC542 = min (MFOR , NTP) If MP <5,0 or NT <5,0
         -------------------------------------------------- ----------------------------------------
NFMC722 = MMC542 se MMC542 > = 5,0
       -------------------------------------------------- ----------------------------------------

invoice = MMC542 se MMC542 Bigger or equal a 5,0

invoice = (MMC542 + EX) / 2 if the student has weighted average
(MMC542) less than 5,0

Jobs

Students must do a Project in the semester.
See the project specification here.

Project: -- Group of up to 06 students

Submit: until 27/04 List of group members
Delivery: until 24:00

The practical exercises and the project must be delivered in the indicated date.

OBS .: The work delivered up to 24 hours after the indicated deadline will not suffer a penalty. After this grace period is over, only the work delivered within 72 hours will be accepted after the indicated deadline, for which there will be a penalty of 30% of the maximum amount.

Recommended VHDL and project documents:

Altera: Recommended HDL Coding Styles

Actel HDL Coding Style Guide

The Ten Commandments of Excellent Design

The Ten Commandments of Excellent Design VHDL Code Examples

Recommended Exercises

Digital Design and Computer Architecture

Chapter 1: 1.4; 1.6 to 1.13; 1.15 to 1.17; 1.19; 1.21; 1.25 to 1.31; 1.33 to 1.36; 1.39; 1.41; 1.42; 1.48 to 1.51; 1.60 to 1.63
Chapter 2: 2.1 to 2.3; 2.7 to 2.9; 2.12 to 2.18; 2.21; 2.24 to 2.26; 2.28 to 2.30; 2.32
Chapter 3: 3.1 to 3.7; 3.9 to 3.12; 3.15 to 3.17; 3.19 to 3.21
Chapter 5: 5.1, 5.3; 5.8; 5.18; 5.20 to 5.29; 5.36 to 5.39; 5.45
Chapter 6: 6.1 to 6.4; 6.8; 6.9; 6.11; 6.12; 6.14; 6.24 to 6.26
Chapter 7: 7.1; 7.3 to 7.6; 7.8; 7.9; 7.12; 7.13; 7.24 to 7.29
Chapter 8: 8.1 to 8.12; 8.15 to 8.21

Fundamentals of Digital Logic with VHDL Design

Chapter 2: 2.1 to 2.27

Chapter 3: 3.1 to 3.13

Chapter 4: 4.1 to 4.20

Chapter 5: 5.1 to 5.10

Chapter 6: 6.1 to 6.17

Chapter 7: 7.1 to 7.24 (skipping VHDL exercises)

Chapter 8: Skip the VHDL

Computer Organization & Design, The Hardware / Software Interface.

Chapter 2: 2.1 to 2.5; 2.10 to 1.13; 2.15 to 2.22; 2.32; 2.44
Chapter 3: 3.1 to 3.6; 3.9; 3.12; 3.16; 3.20;
Cachapter 4: 4.1 to 4.6; 4.13; 4.17; 4.21; 4.23; 4.25 to 4.28; 4.32; 4.33; 4.40; 4.41; 4.43; 4.44; 4.50; 4.53; 4.57
Cachapter 5: 5.1; 5.4; 5.5 to 5.15; 5.17; 5.18; 5.20; 5.21; 5.22; 5.26
Chapter 6: 6.1 to 6.4; 6.7; 6.8; 6.11 to 6.16; 6.19 to 6.26; 6.28 to 6.31
Chapter 7: 7.1 to 7.23; 7.25 to 7.30; 7.32; 7.33; 7.35; 7.36

REFERENCES

Menus

Theory: Basic notions about logic circuits. Memories, central processing units. Addressing, bus, interruption, communications, interfaces and peripherals. Typical computers.
Practice: Digital design methodology. Design techniques using programmable logic. Electrical characteristics of digital circuits. VHDL Language Concepts. Design and implementation of combinational logic (decoders, selectors, etc.). Design and implementation of sequential logic (Flip-flops, Accountants, etc.). Arithmetic circuits. Memories. Design and implementation of a cpu.

Main References

David Harris and Sarah Harris. Digital Design and Computer Architecture. Morgan Kaufmann. ISBN: 978-0-12-370497-9

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. McGraw-Hill.
David A. Patterson & John L. Hennessy. Computer Organization & Design, The Hardware / Software Interface. Third Edition. Morgan Kaufmann.
David A. Patterson & John L. Hennessy. Computer Organization and Design. The Hardware / Software Interface. Third Edition.

Peter J. Ashenden. The VHDL Cookbook.
Actel HDL Coding Style Guide

Other References

M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals🇧🇷 Printece Hall.

John F. Wakerly. Digital Design: Principles & Pratices (second Edition)🇧🇷 Printece Hall.

Herbert Taub. Digital Circuits and Microprocessors. McGraw-Hill.

John P. Uyemura. Digital Systems an integrated approach. Thomson Pioneer.

Mehdi R. Zargham. Computer Architecture: Single and Parallel Systems🇧🇷 Printice Hall.

John P. Hayes. Computer Architecture and Organization. McGraw-Hill Series in Computer Organization and Architecture.

Fredrick J. Hill & Gerald R. Peterson. Digital Logic and Microprocessors. John Wiley & Sons.

Douglas V Hall. Digital Circuits and Systems. McGraw-Hill - Electronic Engineering Series.

Albert P. Malvino. Microcomputers and Microprocessors. Makron.

John L. Hennessy & David A. Patterson. Computer Architecture. The Quantitative Approach. Second Edition. Morgan Kaufmann

Course Program

David M. Harris and Sarah L. Harris. Digital Design and Computer Architecture. Morgan Kaufmann

Chapter 1:
Chapter 2:
Chapter 3:
Chapter 4:
Chapter 5: The VHDL part
Chapter 6:
Chapter 7:
Chapter 8:

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. mcgraw-hil

Chapter 1: Read only
Chapter 2: 2.1-2.7, 2.9.

Chapter 3: 3.1-3.3, 3.8.1, 3.8.3-3.9

Chapter 4: 4.1-4.6, 4.12

Chapter 5: 5.1-5.7

Chapter 6: 6.1-6.6

Chapter 7: 7.1-7.13

Chapter 8: 8.1-8.7
Chapter 9: 9.

David A. Patterson and John L. Hennessy. Computer Organization Design, The Hardware / Software Interface.Morgan Kaufmann

Chapter 1: Read only

Chapter 2: 2.1-2.5 (2.8 and 2.9 - reading)

Chapter 3: 3.1-3.8 (3.9 - reading)

Chapter 4: 4.1-4.8 (does not include the part already seen in logic circuits)

Chapter 5: 5.1-5.6
Chapter 6: 6.1-6.7 (6.8 - reading)
Chapter 7: 7.1-7.5
Chapter 8: 8.1-8.6

Useful links

Altera homepage.

Homepage of the Altera University Program.
Page for obtaining the Altera license
The VHDL Cookbook
Actel HDL Coding Style Guide
VHDL reference material
VHDL Tutorial
GHDL e GTKWAVE (some linux distributions have gtkwave)
SPIM - MIPS simulator
Various simulators and tutorials

Calendar

Aula	Matter
Material and division by class of the last edition of the course (2s2010)
1^a.	Presentation of the Course; Number Systems (pdf pdf-6)
2^a.-3^a.	Number Systems (cont.); Logical Doors, Technology (pdf pdf-6)
4^a.	Logic Doors, Technology (cont.)
5^a.-6^a.	Logic Doors, Technology (cont.); Combinational Circuits Project (pdf pdf-6)
7^a.	Combinational Circuit Design (cont.) - Karnaugh Maps
8^a.-9^a.	Combinational Circuits Project (cont.); Sequential Circuit Design (pdf pdf-6)
10^a	Sequential Circuits; registrars; accountants
11^a.-12^a.	Finite State Machinery Project (pdf pdf-6)
13^a.	Introduction to VHDL (pdf pdf-6)
14^a.-15^a.	Introduction to VHDL Cont. (pdf pdf-6)
16^a.-17^a.	Introduction to VHDL Cont. (pdf pdf-6; pdf pdf-6); In the directory Control there are two .vhd files that will be used as an example of using the Quartus and ghdl and gtkwave tools and in Docs / usage-ghdl.txt a short text with the commands to analyze, elaborate, execute (simulate) and observe the waveforms generated during the example simulation. A tutorial for Quartus can be seen here
18^a.	Elimination of redundant states (pdf pdf-6); More VHDL: flip-flops; registers in state machines (pdf pdf-6)
19^a.-20^a.	Instruction Set - ISA (pdf pdf-6); Lab02
21^a.	Set of Instructions - ISA (cont.); Performance (pdf pdf-6)
22^a.-23^a.	Performance (cont.) - (pdf pdf); Micro architecture - unicycle (pdf pdf-6) (ULA- pdf pdf-6) Laboratory Class: Example of using a more elaborate testebench than just generating input pulses - Copy the contents of the directory Contador_Currencies, read the project specification, execute escripts compila.sh and execute.sh, check the input and output files as well as the testbench code (files tb_contador_base.vhd and tb_contador.vhd).
24^a.	Micro Architecture - Unicycle (cont.)
25^a.-26^a.	Micro architecture - multicycle (pdf pdf-6)
27^a.	Micro architecture - multicycle; Micro architecture - Pipeline (pdf pdf-6);
28^a.-29^a.	Exam 1; lab class
30^a.-31^a	Micro architecture - Pipeline (pdf pdf-6); lab class
32^a.	Micro architecture - Pipeline (Cont.)
33^a.-34^a.	Memory hierarchy (pdf pdf-6); lab class
35^a.	Memory Hierarchy (Cont'd)
36^a.-37^a.	Memory hierarchy (cont.); Lab class
38^a	Memory hierarchy (cont.); Virtual Memory (pdf pdf-6)
39^a.-40^a	Virtual Memory (Cont'd); Lab class
41^a	Exceptions and Advanced Micro-Architectures (pdf pdf-6)
42^a.-43^a.	Advanced Microarchitectures (Cont'd)
44^a	Debts; Lab class
45^a.-46^a.	Lab class - Questions about the project
47^a	Contact - Memory Hierarchy (Cache)
48^a	Contact - Pipeline (Hazard, forwarding, performance)
49^a	Exam 2

Important School Calendar Dates
10/05	Evaluation and discussion of courses
29/04	Last day for dropping out of enrollment
20/05	Last day for registration lock.
08/07	End of term.
11 - 16 / 07	Final exams.
20/07	Deadline for entry of media and frequencies.
Important dates of graduation calendar.

MC 542 - Class # Computer Organization: Theory and Practice

2012

Contact Us

MC 542 - Class #
Computer Organization: Theory and Practice