mc 542
Computer Organization: Theory and practice

classrooms	Project Manager	Review	Exercises	Jobs	REFERENCES	Questions and answers	Calendar	Slides	Students	Notes

Contact Us

Teachers: Paulo Cesar Centoducatte (Email) - Room 11 - IC-1

OBS .: When sending an email please put in the subject "mc542"

Notices

Data	Notices
14/12	Provided the notes of the exam.
10/12	Provided the notes of work. (Exam: 13/12 - CB06 )
08/12	Provided the notes the second test.
29/11	Project: Delivery Date 07/12/2006
22/11	Available to lists of Groups. Please Check
17/11	Vhdl files of the exercise control
17/11	Text with Conversion functions in VHDL
09/11	Available statement of project
03/11	Provided the notes of the first test
29/09	Available tips of ghdl usage and the file for tests
21/09	First statement available Jobs
13/09	Provided a Quartus tutorial
12/09	Provided the slides used in classes until 11/09/2006
25/08	Provided the slides used in classes until 23/08/2006
17/08	Provided the slides used in classes until 16/08/2006

classrooms

Class A
Monday: 16:00 - 18:00 - Room: CB07
Wednesdays:    16:00 - 18:00 - Room: CB06
Fridays:        16:00 - 18:00 - Room: 301 or CC02 (IC-03)

Project Manager

Professor:
Paulo C. Centoducatte: Sala 11

Review

Race 1 (P1): Weight 4 notes

Race 2 (P2): Weight 6

Exercises (Hey)
Project (Prj)
MP - Average of Tests P1 and P2
MTP - Average of Exercises and Project
MMC542 - Final average in the MC542 course
Ex - Final exam grade

MP = (4P1 + 6P2) / 10

$\ begin {displaymath} M_ {TP} = \ frac {\ frac {\ sum_ {1} ^ {n} E_ {i}} {n} + Prj} {2} \ end {displaymath}$

$\ begin {displaymath} M_ {MC542} = \ left \ {\ begin {array} {ll} \ frac {8 M_ {P} + 2 M _ {... ...}; M_ {TP}) & case \ : contr \ acute {a} rio \ end {array} \ right. \ end {displaymath}$

NOTE: If the student has a weighted average (MMC542) less than 5,0 and has a frequency greater than or equal to 75% he will be entitled to take the final exam and the final grade (NF) will be the arithmetic average between the exam grade (Ex) and the average MMC542.

Jobs

Students must do practical exercises and a project in the semester:

1 Exercise: ( pdf )

Delivery fee:

2 Exercise:

Delivery fee:

Project 1: (pdf)

Delivery: 07/12/2006

The practical exercises and the project must be delivered in the indicated date.

NOTE: The work delivered up to 24 hours after the stated period will not suffer penalty. Once this grace period has expired, the work delivered within 72 hours after the indicated deadline will be accepted, for which there will be a 30% penalty the maximum value.

Recommended VHDL and project documents:

Altera: Recommended HDL Coding Styles
Actel HDL Coding Style Guide
The Ten Commandments of Excellent Design
The Ten Commandments of Excellent Design VHDL Code Examples

Exercises

Fundamentals of Digital Logic with VHDL Design

Chapter 2: 2.1 to 2.27

Chapter 3: 3.1 to 3.13

Chapter 4: 4.1 to 4.20

Chapter 5: 5.1 to 5.10

Chapter 6: 6.1 to 6.17

Chapter 7: 7.1 to 7.24 (skipping VHDL exercises)

Chapter 8: Skipping the VHDL

Computer Organization & Design, The Hardware / Software Interface.

Chapter 2: 2.1 to 2.5; 2.10 to 1.13; 2.15 to 2.22; 2.32; 2.44
Chapter 3: 3.1 to 3.6; 3.9; 3.12; 3.16; 3.20;
Cachapter 4: 4.1 to 4.6; 4.13; 4.17; 4.21; 4.23; 4.25 to 4.28; 4.32; 4.33; 4.40; 4.41; 4.43; 4.44; 4.50; 4.53; 4.57
Cachapter 5: 5.1; 5.4; 5.5 to 5.15; 5.17; 5.18; 5.20; 5.21; 5.22; 5.26
Chapter 6: 6.1 to 6.4; 6.7; 6.8; 6.11 to 6.16; 6.19 to 6.26; 6.28 to 6.31
Chapter 7: 7.1 to 7.23; 7.25 to 7.30; 7.32; 7.33; 7.35; 7.36
Chapter 8:

REFERENCES

Menus

Theory: Understanding logic circuits. Memories, central processing units. Addressing, bus, interruption, communications, interfaces and peripherals. Typical computers.
Practice: Digital design methodology. Design techniques using programmable logic. Electrical characteristics of digital circuits. VHDL Language Concepts. Design and implementation of combinational logic (decoders, selectors, etc.). Design and implementation of sequential logic (Flip-flops, Counters, etc.). Arithmetic circuits. Memoirs. Design and implementation of a cpu.

Main References

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. Main ReferencesMcGraw-Hill

David A. Patterson & John L. Hennessy. Computer Organization & Design, The Hardware / Software Interface. Second Edition. Morgan Kaufmann.
David A. Patterson & John L. Hennessy. Computer Organization and Design. The Hardware / Software Interface. Second edition. LTC Editora.

Peter J. Ashenden. The VHDL Cookbook.
Actel HDL Coding Style Guide

Other References

M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals🇧🇷 Printece Hall.

John F. Wakerly. Digital Design: Principles & Pratices (second Edition)🇧🇷 Printece Hall.

Herbert Taub. Digital Circuits and Microprocessors. McGraw-Hill.

John P. Uyemura. Digital Systems an integrated approach. Thomson Pioneer.

Mehdi R. Zargham. Computer Architecture: Single and Parallel Systems🇧🇷 Printice Hall.

John P. Hayes. Computer Architecture and Organization. McGraw-Hill Series in Computer Organization and Architecture.

Fredrick J. Hill & Gerald R. Peterson. Digital Logic and Microprocessors. John Wiley & Sons.

Douglas V Hall. Digital Circuits and Systems. McGraw-Hill - Electronic Engineering Series.

Albert P. Malvino. Microcomputers and Microprocessors. Makron.

John L. Hennessy & David A. Patterson. Computer Architecture. The Quantitative Approach. Second Edition. Morgan Kaufmann

Course Program

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. mcgraw-hil

Chapter 1: Read only
Chapter 2: 2.1-2.7, 2.9.

Chapter 3: 3.1-3.3, 3.8.1, 3.8.3-3.9

Chapter 4: 4.1-4.6, 4.12

Chapter 5: 5.1-5.7

Chapter 6: 6.1-6.6

Chapter 7: 7.1-7.13

Chapter 8: 8.1-8.7
Chapter 9: 9.

David A. Patterson and John L. Hennessy. Computer Organization Design, The Hardware / Software Interface.Morgan Kaufmann

Chapter 1: Read only

Chapter 2: 2.1-2.5 (2.8 and 2.9 - reading)

Chapter 3: 3.1-3.8 (3.9 - reading)

Chapter 4: 4.1-4.8 (does not include the part already seen in logic circuits)

Chapter 5: 5.1-5.6
Chapter 6: 6.1-6.7 (6.8 - reading)
Chapter 7: 7.1-7.5
Chapter 8: 8.1-8.6

Useful links

Altera homepage.

Homepage of the Altera University Program.
Altera license page
The VHDL Cookbook
Actel HDL Coding Style Guide
GHDL e GTKWAVE (some linux distributions have gtkwave)

Calendar

Day	Matter
August
02/08	Introduction to Logical Circuits
04/08	Introduction to Logical Circuits (cont.)
07/08	Implementation Technology of Digital Circuits
09/08	Implementation Technology for Digital Circuits (cont.)
11/08	Implementation of Optimized Logical Functions
14/08	Representation of Numbers and Arithmetic Circuits
16/08	Representation of Numbers and Arithmetic Circuits (cont.)
18/08	Introduction to VHDL Language (Ricardo)
21/08	Combinational Circuits: Basic Blocks
23/08	VHDL for Combination Circuits
25/08	VHDL for Combination Circuits
28/08	Design of Arithmetic Circuits with VHDL
30/08	Flip-Flops, Recorders, Counters
September
Day	Matter
01/09	Flip-Flops, Recorders, Counters
04/09	FF Project, Recorders, VHDL Counters
06/09	Synchronous Sequential Circuits
08/09	There will be no class
11/09	Finite State Machine Design (Basic Concepts and Mealy WSF)
13/09	Finite State Machine Design (Elimination of Redundant States; FSM Mealy)
15/09	Laboratory - Quartus tutorial
18/09	Hazards
20/09	FSM project using VHDL; Introduction to Computer Architecture
22/09	Laboratories
25/09	Instruction Set
27/09	Instruction Set (addressing mode, RISC, CISC, ...)
29/09	Laboratories
October
Day	Matter
02/10	MIPS Instruction Set
04/10	MIPS Instruction Set
06/10	Laboratories
09/10	Race 1 (Monday)
11/10	Computer Arithmetic
13/10	There will be no class
16/10	Computer Arithmetic
18/10	MIPS Datapath Processor and Control Unit - Unicycle
20/10	MIPS Datapath Processor and Control Unit (Mono and Multicycle)
23/10	MIPS Processor - Multicycle
25/10	Pipeline, Hazards, MIPS Pipeline Processor
27/10	MIPS Pipeline Processor
30/10	MIPS Pipeline Processor
November
Day	Matter
01/11	process MIPS - Data Forwarding
03/11	There will be no class
06/11	Proc. MIPS - Data Forwarding and Data Hazard detection
08/11	Hierarchy of Menoria - Basic concepts
10/11	Hierarchy of Menoria - Cache
13/11	Hierarchy of Menoria - Cache
15/11	There will be no class
17/11	Virtual Memory
20/11	There will be no class
22/11
24/11
27/11
29/11
December
Day	Matter
01/12
04/12	Deadline for compliance with the Hours Race 2 (Monday)
06/12
08/12

13/12	Examination
	OBS .: 12 -18 Final exams of the 2nd term

Other Important School Calendar Dates






Holidays

mc 542 Computer Organization: Theory and practice

Contact Us

mc 542
Computer Organization: Theory and practice