17April2026
14:00 Master's Defense Room 85 of IC2
Topic on
Large-Scale Verification of RISC-V Processors
Student
Gabriel Pimentel Gomes
Advisor / Teacher
Rodolfo Jardim de Azevedo
Brief summary
For over five decades, advances in semiconductor technology progressed at the pace predicted by Moore's Law. However, in the early 2000s, manufacturing advancements began to slow, marking the end of predictable scaling. To overcome this problem, designers began investing in microarchitectural diversity and specialization. This new paradigm remained restricted to the few companies holding the predominant Instruction Set Architectures (ISAs), as these were, and still are, aggressively protected as intellectual property. In 2011, the first version of the open-source RISC-V ISA was released, and its adoption allowed other designers, from amateurs to large companies, to develop their own custom processors. This altered the processor development flow, as there are now hundreds of RISC-V implementations available that can be readily incorporated into a new design. Unrestricted access to the open ISA and the need to validate these designs have increased verification efforts by the scientific community. However, these efforts are limited to creating techniques capable of verifying a small set of processors and lack large-scale applicability. To fill this gap, we present the Non-intrusive Trace-Based Verifier (NTV), a tool built on the pillars of reusability and reduced setup time. The first pillar was achieved by limiting the signals used for execution monitoring to generic signals, and the second by introducing automation in testbenche generation. These two characteristics allowed our tool to verify a total of 30 distinct processors—including an out-of-order superscalar—with reduced manual effort, while other works completely lacked automation and verified, at most, 4 cores. The tool compares the execution trace of a Project Under Test (DUT) and the Spike Instruction Set Simulator (ISS) for arbitrary programs. We ran two benchmarks comprising tests for the RV32I base set, one of which is the Official RISC-V Architectural Test Suite. The second benchmark was developed by our team and provided a test case not covered by the official suite, exposing further flaws. A total of 23 bugs were discovered across 13 cores.
Examination Board
Headlines:
| Rodolfo Jardim de Azevedo | IC / UNICAMP |
| Omar Paranaiba Vilela Neto | DCC / UFMG |
| Fabiano Fruett | FEEC / UNICAMP |
Substitutes:
| Allan Mariano de Souza | IC / UNICAMP |
| Ricardo Menotti | DC / UFSCar |