@techreport{TR-IC-13-19,
   number = {IC-13-19},
   author = {Liana Duenha and Rodolfo Azevedo},
   title   =   {{MPSoCBench:   A   Benchmark   Suite   for  Evaluating 
                   Multiprocessor     System-on-Chip     Tools     and    
                   Methodologies}},
   month = {August},
   year = {2013},
   institution = {Institute of Computing, University of Campinas},
   note = {In English, 29 pages.
    \par\selectlanguage{english}\textbf{Abstract}
       The consolidated use of multiprocessors in the embedded systems
       designs   introduces   new   important  challenges  for  system 
       architects  and  hardware/software designers. In particular, it
       becomes necessary to develop tools based on new paradigms, able
       to  deal  with  MPSoC complexities. Recent design methodologies
       and  tools  are focused on enhancing the design productivity by
       providing  a  software  development  platform  before the final
       MPSoC  architecture  details are fixed. However, the simulation
       can  only  be efficiently implemented when using a modeling and
       simulation engine that supports the system behavior description
       in  a  high  abstraction  level.  The  lack  of  multiprocessor 
       platforms  integrating  both  scalable hardware and software in
       order  to  design  and  evaluate  new  methodologies  and tools
       motivated  us  to  develop  MPSoCBench,  which  is  a benchmark
       composed  by  a scalable set of MPSoCs including four different
       ISAs  (PowerPC,  MIPS,  SPARC, and ARM), organized in platforms
       with  1,  2,  4,  8,  16,  32,  or  64  cores,  with  different 
       interconnections  (router  or  NoCs),  capable  of  running  13 
       parallel   version   of   software  from  well  known  parallel 
       benchmarks.  The tool also provide power consumption estimation
       for  MIPS and SPARC processors. The benchmark sums 828 distinct
       configurations automated through scripts.
  }
}