@techreport{TR-IC-97-21,
  number = {IC-97-21},
  author = {Araújo, Guido and Malik, Sharad},
  title = {Code Generation for {Dual-Load-Execute} Architectures},
  month = {November},
  year = {1997}, 
  institution = {Institute of Computing, University of Campinas},
  note = {In English, 25 pages.
    \par\selectlanguage{english}\textbf{Abstract}
      This paper studies the problem of register allocation and
      scheduling for {\em Dual-Load-Execute} (DLE) architectures.
      These are architectures which can execute an ALU instruction and
      two memory transfer operations ({\em load/store}) in a single
      instruction cycle.  DLE architectures are extensively used in
      the design of {\em Digital Signal Processors} (DSPs) like the
      Motorola 56000, Analog Devices ADSP-2100, and NEC
      $\mu$PD77016. This work proves the existence of an efficient
      $O(n)$ expression tree code generation algorithm for DLE
      architectures which have homogeneous register sets. The
      algorithm is an extension of the Sethi-Ullman algorithm, and
      produces guaranteed optimal code for a large number of
      expression trees in the program. The experimental results, using
      the NEC $\mu$PD77016 as the target processor, show the efficacy
      of the approach.
  }
}