@techreport{TR-DCC-93-19,
  number = {DCC-93-19},
  author = {Krüger, Carlos G. and Côrtes, Mário L.},
  title = {Modelamento, Simulação e Síntese com {VHDL}},
  month = {September},
  year = {1993}, 
  institution = {Department of Computer Science, University of Campinas},
  note = {In Portuguese, 20 pages.
    \par\selectlanguage{english}\textbf{Abstract}
      This paper discusses the use of VHDL as a language for modeling,
      simulating, and synthesizing integrated circuits, and the language
      suitability to each of these tasks. It also discusses the problems
      related to the transition between different levels of abstraction
      to obtain a synthesizable VHDL model.
  }
}